Features：
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.27 GHz to 2.65 GHz
Auto and manual reference switchover/holdover modes
Zero delay operation optional
Twelve 1.6 GHz LVPECL/CMOS outputs divided into four groups
Each group of 4 has a 1 to 32 divider with phase delay
SPI- and I2C-compatible control port
Nonvolatile EEPROM stores configuration settings
The AD9520-11 provides a multioutput clock distribution function with sub-picosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.
The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.
The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V
The AD9520 is specified for operation over the standard industrial range of −40°C to +85°C.
1 The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-1 is used, it is referring to that specific member of the AD9520 family.
ApplicationsLow jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
